IBM has partnered with Siemens to advance nanostack, the three-dimensional transistor architecture it unveiled earlier this year, as the pair work to prepare the design for manufacturing at scale.
Nanostack vertically stacks and staggers transistors, fitting nearly 100 billion transistors into a fingernail-sized footprint at its current 7 angstrom node, and allows different materials within each layer to tune performance and power independently.
The collaboration pairs IBM's semiconductor device engineering with Siemens' electronic design automation, process simulation and lithography optimization software, building virtual models of nanostack to test performance and flag fabrication problems before chips are physically built.
IBM demonstrated nanostack's viability earlier this year. The work now shifts to design, simulation and lithography techniques needed for this and future generations beyond the 7 angstrom node.
"Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry," said Huiming Bu, IBM's vice president of silicon technology research and development.
Siemens' Ankur Gupta, executive vice president of its EDA IC portfolio, said scaling semiconductors into the angstrom era "demands tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing."
He called IBM's 3D design "a pivotal leap forward" as physical AI raises the bar for silicon architecture.
